| Code | Project Title | Year |
|---|---|---|
| VLP01 | A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging | IEEE 2017-18 |
| VLP02 | Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture | IEEE 2017-18 |
| VLP03 | Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding | IEEE 2017-18 |
| VLP04 | A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption | IEEE 2017-18 |
| VLP05 | Resource-Efficient SRAM-based Ternary Content Addressable Memory | IEEE 2017-18 |
| VLP06 | Write-Amount-Aware Management Policies for STT-RAM Caches | IEEE 2017-18 |
| VLP07 | Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA | IEEE 2017-18 |
| VLP08 | High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder | IEEE 2017-18 |
| VLP09 | High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations | IEEE 2017-18 |
| VLP10 | Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST | IEEE 2017-18 |
| VLP11 | Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map | IEEE 2017-18 |
| VLP12 | Efficient Designs of Multi-ported Memory on FPGA | IEEE 2017-18 |
| VLP13 | High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA | IEEE 2017-18 |
| VLP14 | An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock | IEEE 2017-18 |
| VLP15 | A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique | IEEE 2017-18 |
| VLP16 | Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares | IEEE 2017-18 |
| VLP17 | Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm | IEEE 2017-18 |
| VLP18 | A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission | IEEE 2017-18 |
| VLP19 | Scalable Device Array for Statistical Characterization of BTI-Related Parameters | IEEE 2017-18 |
| Code | Project Title | Year |
|---|---|---|
| VAE01 | VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding | IEEE 2017-18 |
| VAE02 | ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware | IEEE 2017-18 |
| VAE03 | Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs | IEEE 2017-18 |
| VAE04 | Efficient Soft Cancelation Decoder Architectures for Polar Codes | IEEE 2017-18 |
| VAE05 | Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition | IEEE 2017-18 |
| VAE06 | Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication | IEEE 2017-18 |
| VAE07 | FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers | IEEE 2017-18 |
| VAE08 | Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields | IEEE 2017-18 |
| VAE09 | Antiwear Leveling Design for SSDs With Hybrid ECC Capability | IEEE 2017-18 |
| VAE10 | Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems | IEEE 2017-18 |
| Code | Project Title | Year |
|---|---|---|
| VAIVP01 | A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding | IEEE 2017-18 |
| VAIVP02 | RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy- Efficient Digital Signal Processing | IEEE 2017-18 |
| VAIVP03 | Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations | IEEE 2017-18 |
| VAIVP04 | Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers | IEEE 2017-18 |
| VAIVP05 | An FPGA-Based Hardware Accelerator for Traffic Sign Detection | IEEE 2017-18 |
| VAIVP06 | Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations | IEEE 2017-18 |
| VAIVP07 | Time-Encoded Values for Highly Efficient Stochastic Circuits | IEEE 2017-18 |
| VAIVP08 | Design of Power and Area Efficient Approximate Multipliers | IEEE 2017-18 |
| Code | Project Title | Year |
|---|---|---|
| VVF01 | COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits | IEEE 2017-18 |
| VVF02 | Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction | IEEE 2017-18 |
| Code | Project Title | Year |
|---|---|---|
| VBEP01 | Temporarily Fine-Grained Sleep Technique for Near- and Sub-threshold Parallel Architectures | IEEE 2017-18 |
| VBEP02 | Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique | IEEE 2017-18 |
| VBEP03 | 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage | IEEE 2017-18 |
| VBEP04 | Delay Analysis for Current Mode Threshold Logic Gate Designs | IEEE 2017-18 |
| VBEP05 | Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications | IEEE 2017-18 |
| VBEP06 | Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating | IEEE 2017-18 |
| VBEP07 | A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications | IEEE 2017-18 |
| VBEP08 | A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS | IEEE 2017-18 |
| VBEP09 | Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application | IEEE 2017-18 |
| VBEP10 | An All-MOSFET Sub-1-V Voltage Reference With a−51-dB PSR up to 60 MHz | IEEE 2017-18 |
| VBEP11 | A 65-nm CMOS Constant Current Source with Reduced PVT Variation | IEEE 2017-18 |
| VBEP12 | A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy | IEEE 2017-18 |
| VBEP13 | Preweighted Linearized VCO Analog-to-Digital Converter | IEEE 2017-18 |
| VBEP14 | A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression | IEEE 2017-18 |
| VBEP15 | Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template | IEEE 2017-18 |
| VBEP16 | On Micro-architectural Mechanisms for Cache Wear out Reduction | IEEE 2017-18 |
| VBEP17 | Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology | IEEE 2017-18 |
| VBEP18 | A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing | IEEE 2017-18 |
| VBEP19 | A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures | IEEE 2017-18 |
